A compressed, long-form version of the original essay (https://thesovereignpulse.blogspot.com/2026/09/the-open-silicon-decade-how-dholera.html) — designed as a durable reference point for the open-silicon story unfolding around India’s semiconductor ecosystem.
What if we look back from 2030?
Imagine it is December 2030.
India's semiconductor industry is no longer described primarily as an ambitious national project. Chips are being designed, fabricated, packaged and deployed at meaningful scale. Dholera is no longer just a construction site or symbol of semiconductor sovereignty. It is one node in a larger Indian design-and-manufacturing ecosystem.
And somewhere in that ecosystem, a curious thing has happened.
A meaningful share of the silicon running Indian products did not begin life inside the walls of a proprietary semiconductor company.
Some of it began on GitHub.
A RISC-V processor core. An accelerator. A GPU architecture. A video codec. A camera ISP. A PCIe controller. An NVMe controller. A security subsystem. A SoC interconnect. A complete RTL-to-GDS flow.
Engineers combined these building blocks, modified them, verified them, added proprietary pieces where necessary, and eventually turned them into masks and silicon.
That is the possibility worth examining today.
The most interesting consequence of Dholera may not be that India finally has a domestic semiconductor fab. It may be that India acquires a domestic silicon development loop — a loop in which open hardware, Indian university research, RISC-V, commercial IP, EDA tools, manufacturing, packaging and software increasingly reinforce one another.
There is no guarantee that this happens.
But the ingredients are beginning to exist.
Dholera is the manufacturing anchor
The starting point is the planned Tata Electronics semiconductor fab at Dholera, Gujarat, being developed in partnership with Taiwan's Powerchip Semiconductor Manufacturing Corporation, or PSMC.
The current official description is important because it establishes the boundary between what is real today and what remains a future possibility.
Tata describes the facility as a 300mm fab with planned capacity of up to 50,000 wafers per month, initially targeting analogue and logic chips across the 28nm to 110nm range. Its intended markets include automotive, computing and data storage, wireless communication, IoT and other applications. :contentReference[oaicite:0]{index=0}
That is already strategically significant.
But this article is interested in a slightly different question:
What happens if, during the second half of this decade, India's manufacturing and design ecosystem begins moving toward 22nm-class open-silicon designs?
That is a scenario, not a current Dholera commitment.
Likewise, discussion of FD-SOI should not be mistaken for an announcement that Dholera will become a 22nm FD-SOI fab. The present public technology plan is 28nm–110nm. Any future move to 22nm FD-SOI would require substantial process-development, PDK, IP, SRAM, device, materials and manufacturing work.
But the distinction matters because 28nm, 22nm and FD-SOI are not merely numbers on a roadmap.
They determine which kinds of computing architectures become economically attractive.
The real opportunity is the stack
It is tempting to frame semiconductor sovereignty as a race to build an Indian processor.
That is too narrow.
A modern chip is not just a CPU core.
A practical SoC needs memory controllers, interconnects, caches, DMA engines, interrupt controllers, timers, security, boot ROM, debug, storage interfaces, PCIe, USB, Ethernet, display interfaces, accelerators and often analogue or RF components.
Then comes the software:
- boot firmware
- device drivers
- operating-system support
- compilers
- debugging tools
- performance libraries
- AI frameworks
- graphics drivers
- applications
And beneath all of that is the manufacturing layer:
- PDKs
- standard-cell libraries
- SRAM compilers
- IO libraries
- physical-design flows
- verification
- timing closure
- packaging
- testing
This is why open silicon is potentially much more important than an open CPU.
Open silicon allows developers to assemble a technology stack.
RISC-V supplies an open instruction-set architecture. Projects such as SHAKTI, CVA6, BlackParrot, Ibex and VexRiscv provide processor implementations. Vortex explores open GPGPU architecture. Coral NPU and NVDLA explore neural acceleration. Fudan's OpenASIC projects demonstrate open video-processing hardware. Infinite-ISP addresses image processing. OpenTitan addresses hardware security. LiteX and related cores provide SoC infrastructure. OpenROAD and similar projects attack the physical implementation problem.
No single project solves the semiconductor problem.
Collectively, however, they begin to resemble a toolkit.
RISC-V is the critical common language
One clarification is essential.
RISC-V is not a processor.
It is an open instruction-set architecture.
That distinction is enormously important.
An ISA defines the language understood by a processor. Different organisations can build radically different CPUs that implement the same RISC-V ISA.
That means an Indian company does not have to design an instruction-set architecture from scratch merely to own its processor technology.
It can build a processor compatible with a global open standard and differentiate elsewhere: microarchitecture, cache hierarchy, vector engines, security, accelerators, packaging, power management, software or application-specific features.
India's Digital India RISC-V, or DIR-V, programme has already positioned RISC-V as an important component of the country's indigenous processor strategy, including projects such as SHAKTI and VEGA.
The strategic advantage is therefore not simply that RISC-V is royalty-free.
It is that RISC-V makes processor development composable.
SHAKTI proves that India can go beyond RTL
The most important Indian project in this story is arguably SHAKTI from IIT Madras.
SHAKTI is not merely a research CPU. Its stated objective is an open-source processor ecosystem spanning processors, SoCs and peripheral IP, with its components released under a three-part BSD licence. Its processor family ranges from embedded designs to higher-performance application and enterprise-oriented processors. :contentReference[oaicite:1]{index=1}
The most important historical evidence is even more concrete.
SHAKTI's RISECREEK test chip was fabricated on Intel's 22nm FinFET process. The chip used a 64-bit RISC-V C-Class processor, was packaged in BGA, and successfully booted RISC-V Linux. The reported design closed at 350MHz and contained approximately 370,000 SoC gates. :contentReference[oaicite:2]{index=2}
That fact changes the conversation.
India has already demonstrated that an open Indian processor design can travel from university research to physical silicon at 22nm.
The question for the 2030s is no longer whether this is technically possible.
The question is whether such capability can become repeatable, commercial and scalable.
The 22nm lesson
SHAKTI's 22nm tapeout is particularly interesting because it provides a bridge between open hardware and the sort of process technology often associated with modern embedded computing.
But one should not make the simplistic argument that a previous 22nm tapeout means Dholera can automatically fabricate the same design.
A chip design is tightly coupled to its process technology.
The PDK, standard cells, SRAM macros, IO cells, PLLs, memory compilers, design rules and physical-design methodology all matter.
A design that works on Intel's 22nm process does not automatically drop into a hypothetical Dholera 22nm process.
What the SHAKTI result demonstrates is something more fundamental:
Indian teams already understand the path from open RTL to real silicon at a relatively advanced node.
That institutional knowledge may ultimately be more valuable than the individual chip.
The FD-SOI wildcard
There is another technology worth watching closely: FD-SOI.
GlobalFoundries' 22FDX platform is perhaps the best-known example.
Unlike FinFET, 22FDX is a planar, fully depleted silicon-on-insulator technology. GlobalFoundries designed it to combine performance, power efficiency and cost advantages, particularly for IoT, mobile, RF, networking and edge applications. The company highlighted 0.4V operation, body-bias control and substantial power and die-size advantages relative to older 28nm technologies. :contentReference[oaicite:3]{index=3}
The technology has also been used commercially at significant scale. GlobalFoundries said its 22FDX platform had shipped more than 350 million chips by 2020 and had generated billions of dollars in design wins. :contentReference[oaicite:4]{index=4}
Why does that matter to India?
Because it demonstrates that 22nm does not necessarily mean FinFET complexity.
FD-SOI can be attractive for chips where power efficiency, analogue integration, RF, embedded intelligence and cost matter more than absolute leading-edge density.
It is particularly interesting for the sort of computing that India is likely to need in enormous volumes:
- industrial controllers
- automotive electronics
- wireless devices
- edge AI
- IoT
- smart cameras
- routers
- storage controllers
- microservers
- embedded computers
But FD-SOI is not a simple upgrade to ordinary bulk CMOS.
A hypothetical Dholera transition would require SOI wafers, new process integration, device models, PDKs, standard cells, SRAM, analogue IP, RF IP, libraries and qualification infrastructure.
So the right way to describe FD-SOI is not “the obvious next node for Dholera.”
It is better described as a strategically interesting branch of the possible Indian semiconductor roadmap.
Europe provides another piece of the puzzle
India does not have to build this ecosystem alone.
Europe has been developing its own open-computing infrastructure, and the connection is increasingly interesting.
The European eProcessor project demonstrated an open RISC-V ecosystem with a 64-bit out-of-order processor, accelerators and Linux-capable FPGA prototypes. Most importantly, the project resulted in an ASIC fabricated at GlobalFoundries' 22nm process. European reporting described it as a first European out-of-order RISC-V processor fabricated in silicon at 22nm. :contentReference[oaicite:5]{index=5}
That creates an interesting India-Europe axis.
Europe brings deep semiconductor expertise, research institutions, equipment companies and advanced chip-design capability.
India brings a huge engineering workforce, growing electronics demand, RISC-V programmes, university research and an emerging manufacturing base.
The Netherlands is particularly significant because of ASML and the wider Dutch semiconductor ecosystem.
Tata Electronics and ASML announced a strategic partnership in 2026 covering lithography tools, fab ramp-up, training, local skills and R&D infrastructure for Dholera. :contentReference[oaicite:6]{index=6}
That relationship should be viewed as more than an equipment transaction.
It connects India to one of the most sophisticated semiconductor ecosystems on Earth.
And it creates a plausible pathway for collaboration between Indian universities, European research institutions, equipment companies and Indian manufacturing.
The accelerator layer is where things become interesting
Once a RISC-V CPU becomes relatively accessible, the next question is obvious:
What do you put beside it?
This is where open accelerator projects become important.
Coral NPU
Google's Coral ecosystem provides an important distinction between proprietary silicon and open architecture.
The original Coral Edge TPU is a proprietary Google accelerator. But Google's newer Coral NPU architecture is explicitly intended as open-source IP for silicon partners. It is RISC-V based and released under Apache 2.0. The published architecture targets scalar, vector and matrix computation, with a design point aimed at roughly 512 GOP/s and low-power operation at 22nm. :contentReference[oaicite:7]{index=7}
This is precisely the kind of IP that could become useful in an Indian SoC ecosystem.
A domestic chip does not necessarily need a gigantic GPU.
It may need a modest CPU plus a highly efficient neural accelerator.
NVDLA and Gemmini
NVIDIA's NVDLA project provides another example of open accelerator architecture. It is designed as a configurable deep-learning accelerator with RTL, simulation and verification infrastructure.
Berkeley's Gemmini takes another approach, providing a configurable systolic-array accelerator generator suitable for machine-learning workloads.
These projects illustrate an important future model:
The processor may become the coordinator while specialised accelerators handle the workloads that actually consume most of the energy.
The open GPU problem
The GPU is considerably harder.
There are open graphics and compute architectures, but GPUs are not merely collections of arithmetic units. A usable GPU requires memory management, command processing, compiler infrastructure, APIs, drivers, graphics pipelines and years of software optimisation.
That is why Vortex is so interesting.
Vortex is an open-source RISC-V GPGPU architecture with simulator, RTL and FPGA implementations. Its ecosystem has expanded substantially, including graphics functionality, tensor-oriented features, memory-management capabilities and software-stack work. Recent versions have also added more conventional graphics-pipeline functionality and Vulkan-related infrastructure. :contentReference[oaicite:8]{index=8}
It should not be confused with a drop-in replacement for an AMD or NVIDIA gaming GPU.
But it demonstrates something important:
The architecture of a programmable parallel processor can exist outside the traditional proprietary GPU ecosystem.
Could an open GPU reach 1 TFLOPS?
This is one of the more interesting thought experiments for 2030.
Suppose an open GPU architecture currently demonstrated primarily through FPGA implementations is scaled substantially using a suitable ASIC process.
At a high level, 1 TFLOPS of FP32 performance requires roughly one trillion floating-point operations per second.
That is no longer an absurd number for an ASIC.
But it would be a mistake to translate “1 TFLOPS” directly into “gaming GPU.”
Gaming performance depends on far more than arithmetic throughput.
- memory bandwidth matters
- cache architecture matters
- texture performance matters
- rasterisation matters
- driver maturity matters
- Vulkan/OpenGL support matters
- shader compilation matters
- CPU performance matters
- game-engine compatibility matters
- anti-cheat and application compatibility matter
A 1-TFLOPS open GPU could therefore be a fascinating accelerator without being a competitive gaming GPU.
Nevertheless, the trajectory matters.
If open GPU architectures become sufficiently mature by 2030, India could theoretically build SoCs containing a RISC-V CPU, an open vector unit, a neural accelerator and a programmable GPU — all assembled around an open architecture rather than licensed as a monolithic proprietary design.
Video is another surprisingly important opportunity
One of the most interesting projects outside the better-known RISC-V world comes from Fudan University's ASIC and video-processing research ecosystem.
Fudan's OpenASIC work includes open H.264 and H.265 hardware IP. Its xk265 project, for example, provides RTL for an H.265 encoder and targets applications including 4K video. Fudan's research group has also demonstrated silicon-proven video-processing hardware. :contentReference[oaicite:9]{index=9}
This is strategically important because video codecs are exactly the sort of functionality that benefits from hardware acceleration.
A domestic camera, surveillance system, automotive computer or media appliance does not need a gigantic general-purpose CPU to encode and decode video.
It needs dedicated hardware.
And that hardware can sit next to a RISC-V CPU.
The camera could become another open-silicon domain
India's electronics ecosystem is already deeply involved in smartphones, cameras, automotive electronics and surveillance.
That makes image processing another logical target.
Projects such as Infinite-ISP demonstrate that an open-source image signal processor can be developed for ASIC and FPGA use.
The implications are considerable.
A future Indian smart-camera SoC could potentially combine:
- SHAKTI or another RISC-V CPU
- an open ISP
- a neural accelerator
- video encode/decode hardware
- security hardware
- LPDDR or other memory interfaces
- Ethernet or wireless connectivity
That is much more commercially plausible than attempting to build an Indian equivalent of the entire smartphone application-processor industry on day one.
Storage is another missing piece
The open-hardware ecosystem also contains work on storage.
IIT Madras has previously demonstrated an open NVMe controller implementation capable of running on Xilinx FPGA platforms. OpenSSD projects have similarly explored open SSD controller firmware and hardware platforms.
The significance is easy to underestimate.
Storage controllers are everywhere.
They sit inside SSDs, servers, embedded systems and data-centre infrastructure.
They are exactly the kind of specialised silicon where an open design could be valuable if the verification, NAND interface and firmware ecosystem mature sufficiently.
In other words, open silicon does not have to begin with glamorous processors.
Some of the first successful products could be extraordinarily boring.
And that is a good thing.
The boring IP may be the most valuable IP
Every SoC needs infrastructure.
Projects such as LiteX provide SoC-building infrastructure and a large ecosystem of interfaces. LitePCIe provides PCIe functionality. LiteSATA handles SATA. LiteSDCard handles SD-card interfaces. Other open projects cover Ethernet, HDMI and additional peripherals.
These are not headline-grabbing technologies.
But they reduce the amount of proprietary engineering that has to be recreated for every chip.
That is exactly what an ecosystem needs.
Open hardware becomes powerful when developers stop having to reinvent the same blocks repeatedly.
The objective is therefore not to find one miraculous open-source processor.
It is to create a library of reusable, verified building blocks.
Connectivity remains difficult
Wireless is a particularly important warning.
OpenWiFi demonstrates that open FPGA-based digital/baseband implementations of Wi-Fi are possible. But a commercially deployable wireless chip also needs RF circuitry, analogue components, calibration, power management, packaging, certification and a mature software stack.
Similarly, an open HDMI implementation does not eliminate all commercial licensing and compliance considerations associated with HDMI products.
USB, PCIe and Ethernet are much more approachable than an entire cellular modem.
This distinction matters because open hardware enthusiasts sometimes underestimate the non-digital parts of semiconductor design.
Opening the RTL does not automatically open the entire chip.
RF, analogue, memory, PHYs, SerDes and certain interface technologies remain major barriers.
Security could become an open layer
OpenTitan is perhaps the clearest example of why hardware security belongs in this discussion.
It is an open-source silicon Root of Trust platform designed to provide secure boot, cryptographic functionality and hardware security infrastructure.
For India, the significance is strategic.
A domestic SoC does not merely need an open CPU.
It needs to establish trust in the boot chain, firmware, keys and security-critical hardware.
An open security architecture makes independent verification possible in ways that are much harder with completely opaque proprietary subsystems.
What would a 2030 open-silicon stack actually look like?
The most useful way to think about the opportunity is as a layered stack.
| Layer | Examples | 2030 role |
|---|---|---|
| ISA | RISC-V | Common processor architecture |
| CPU | SHAKTI, CVA6, BlackParrot, Ibex, VexRiscv | Application, embedded and control compute |
| Vector | Ara and related PULP work | SIMD/vector workloads |
| GPU | Vortex and other research architectures | Parallel compute and potentially graphics |
| NPU | Coral NPU, NVDLA, Gemmini | AI inference |
| Video | Fudan OpenASIC | H.264/H.265 acceleration |
| ISP | Infinite-ISP | Camera/image processing |
| Storage | IITM NVMe, OpenSSD | SSD and data-storage controllers |
| Security | OpenTitan | Root of Trust |
| SoC infrastructure | LiteX and related cores | Interconnect and peripheral integration |
| Interfaces | LitePCIe, LiteSATA, LiteSDCard, Ethernet, HDMI | Peripheral connectivity |
| Wireless | OpenWiFi | Open digital/baseband experimentation |
| Physical design | OpenROAD, OpenLane | RTL-to-GDS implementation |
| Verification | Verilator and open verification ecosystems | Simulation and validation |
| Software | Linux, Zephyr, Ubuntu | Operating systems and applications |
The table is not a claim that every component is production-ready.
That distinction is essential.
Some projects are mature enough for commercial use. Some have silicon evidence. Some are FPGA-proven. Some remain primarily research projects.
The opportunity lies in moving projects upward through the maturity ladder.
The maturity ladder
Open silicon should be evaluated through several stages:
- Concept — architecture and research paper.
- RTL — synthesizable implementation exists.
- FPGA — hardware has been demonstrated on programmable logic.
- ASIC synthesis — physical implementation is feasible.
- Tapeout — design has become silicon.
- Functional silicon — fabricated chip actually works.
- Production — repeatable manufacturing exists.
- Product — customers buy it and software supports it.
This is the discipline the open-silicon movement needs.
A GitHub repository is not a chip.
An FPGA demonstration is not a production SoC.
A tapeout is not a product.
And a working chip without drivers is not a computing platform.
The real achievement will be moving open projects through the entire chain.
That is where Dholera becomes strategically important
A domestic fab changes the economics of experimentation.
Without a domestic manufacturing base, an Indian university or startup can design silicon but remains dependent on foreign foundries for fabrication.
With a domestic fab, the possibility emerges of a more integrated loop:
Research → RTL → verification → physical design → tapeout → Dholera → packaging → software → product.
That loop could be extraordinarily valuable.
It would allow Indian universities to work on real manufacturing constraints rather than purely theoretical architectures.
It would allow startups to prototype application-specific chips without building an entire semiconductor manufacturing operation.
It would allow the government to fund reusable IP rather than repeatedly funding isolated chip projects.
And it would allow the manufacturing ecosystem to learn which open IP is actually robust enough for commercial silicon.
The EDA problem is just as important
Open hardware is meaningless if designers cannot turn RTL into manufacturable layouts.
This is why OpenROAD matters.
OpenROAD is an open RTL-to-GDS flow intended to automate and simplify the physical implementation process.
It does not eliminate commercial EDA tools. Nor should it be portrayed as a magical replacement for Synopsys, Cadence or Siemens EDA.
But it demonstrates that more of the chip-design toolchain can become open and reproducible.
That matters for universities.
It matters for startups.
It matters for experimentation.
And eventually it matters for national capability.
India should therefore think about semiconductor sovereignty at two levels:
- manufacturing sovereignty — the ability to fabricate domestically
- design sovereignty — the ability to create, modify and verify the IP used in those chips
Neither is sufficient alone.
Software will determine whether the hardware matters
This may ultimately be the most important point in the entire argument.
Hardware is useless without software.
RISC-V has already gained substantial software support, and Linux is central to making application-class RISC-V hardware practical.
Canonical has been expanding Ubuntu support for RISC-V and describes the architecture as an important open platform for future computing. Current Ubuntu documentation supports riscv64, with newer releases aligning with increasingly capable RISC-V platform profiles.
That creates an opportunity for India.
Imagine a 2030 Indian RISC-V workstation or development board that boots Ubuntu, runs GCC and LLVM, supports containers, compiles mainstream software and exposes open accelerator APIs.
It does not have to beat an Apple M-series processor or an AMD Ryzen CPU on every benchmark.
It simply needs to be good enough, open enough and available enough to create a developer ecosystem.
Once developers target the platform, hardware improvement becomes much easier to justify.
Could there be an Indian RISC-V laptop?
By 2030, this is entirely plausible as an ecosystem experiment.
A hypothetical Indian laptop SoC could contain:
- a multi-core RISC-V CPU
- a vector engine
- a modest GPU
- a neural accelerator
- video decode/encode
- display controllers
- PCIe
- USB
- security hardware
- memory controllers
The first generation would probably not compete directly with the best x86 or ARM laptop processors.
But that is not the correct benchmark.
The first benchmark should be whether the platform can support real Indian developers and institutions.
Can it run Linux?
Can it compile software?
Can it browse the web?
Can it run development environments?
Can it support AI inference?
Can students inspect the hardware?
Can startups modify the SoC?
Can a government department deploy it without depending entirely on a foreign processor roadmap?
If the answer becomes yes, the strategic value is already substantial.
And smartphones?
Smartphones are a much harder target.
A modern smartphone application processor integrates an extraordinary amount of IP: CPU, GPU, NPU, ISP, video, display, memory, modem, security, power management and high-speed interfaces.
The cellular modem alone is a massive challenge.
Therefore, “India will build a fully open smartphone chip by 2030” is not a sensible baseline assumption.
A more credible path is incremental:
- embedded controllers
- industrial SoCs
- automotive controllers
- edge-AI chips
- storage controllers
- network processors
- development boards
- servers and accelerators
- eventually, more integrated consumer SoCs
The semiconductor industry is built through accumulated competence.
It is rarely created by jumping directly to the hardest possible product.
What India should actually build
This leads to a policy conclusion that is different from the usual semiconductor narrative.
India should not try to build the Indian CPU.
It should try to build the Indian open silicon ecosystem.
That means funding infrastructure rather than only flagship chips.
Imagine a national programme with the following components:
- open RISC-V cores
- open accelerator IP
- open peripheral IP
- open verification infrastructure
- PDK access for universities and startups
- standard-cell and SRAM libraries
- reusable chiplets
- shared test-chip programmes
- shared MPW shuttle runs
- commercial-quality documentation
- Linux and compiler support
- long-term maintenance funding
The objective would be to create something closer to an open semiconductor commons.
A university team could build a new accelerator.
A startup could integrate it into an SoC.
A design house could optimise the physical implementation.
A fab could manufacture it.
An OS vendor could support it.
And a product company could commercialise it.
That is an ecosystem.
The biggest mistake would be to confuse openness with free
Open-source hardware does not mean semiconductor development becomes cheap.
Verification remains expensive.
Physical design remains difficult.
Packaging remains expensive.
Wafer runs cost money.
High-speed PHYs are difficult.
SRAM is difficult.
Analogue design is difficult.
RF is difficult.
Certification is difficult.
Software maintenance is difficult.
The economic advantage of open silicon is therefore not “free chips.”
It is shared development.
One organisation builds a verified component. Others can use it.
One university develops a compiler backend. Others benefit.
One company validates an interconnect. Others do not have to start from zero.
That is how software ecosystems achieved extraordinary leverage.
The long-term question is whether some of that leverage can move downward into hardware.
Why 2030 is a useful deadline
2030 is close enough to force realism and far enough away for ecosystems to compound.
By then, today's research repositories will have had several years to mature.
Today's FPGA projects could become ASIC projects.
Today's ASIC projects could become products.
Today's university researchers could become startup founders.
Today's students could become the engineers designing the next generation of Indian SoCs.
And today's Dholera fab could have evolved from a first manufacturing operation into a platform around which additional design and manufacturing capabilities have accumulated.
The most important metric in 2030 should therefore not be:
“How many chips did India manufacture?”
It should be:
“How many complete semiconductor products can Indian engineers take from architecture to working silicon?”
That is a much more meaningful measure of technological sovereignty.
The 2030 scorecard
If we were writing the retrospective in 2030, the open-silicon experiment should be judged on a few simple questions.
| Question | What success would look like |
|---|---|
| RISC-V | Multiple Indian commercial processors and SoCs |
| SHAKTI | Production-grade processors beyond academic demonstrations |
| AI | Domestic RISC-V SoCs with competitive edge-AI accelerators |
| GPU | Open programmable graphics/compute silicon with usable software |
| Video | Open codec IP used in commercial products |
| ISP | Open image-processing blocks integrated into camera SoCs |
| Storage | Open controller technology reaching commercial SSD/storage products |
| Security | Open Root-of-Trust technology deployed at scale |
| EDA | Open flows routinely used for research and selected production designs |
| Software | Linux/Ubuntu and developer tooling treated as first-class RISC-V platforms |
| Manufacturing | Dholera supporting repeated domestic tapeouts and commercial production |
| Ecosystem | Universities, startups, fabs and global technology companies sharing development |
The deeper geopolitical significance
Semiconductor sovereignty is often presented as a competition between countries.
But the more important competition may be between closed dependency and technological optionality.
India will continue to use processors designed abroad.
It will continue to use ARM-based systems.
It will continue to buy x86 servers.
It will continue to use NVIDIA GPUs and proprietary networking hardware.
None of that contradicts semiconductor sovereignty.
Sovereignty does not mean refusing foreign technology.
It means having alternatives when strategic circumstances require them.
An Indian company that can design a RISC-V SoC has more options than one that cannot.
An Indian university that can modify a processor has more options than one that can only buy it.
A country with domestic fabrication has more options than one completely dependent on overseas fabs.
A country with domestic packaging and testing has more options than one dependent on foreign assembly.
And an ecosystem that can combine open IP with proprietary IP has more options than one locked into a single vendor.
Optionality is the real meaning of sovereignty.
The Dholera opportunity is therefore larger than the fab
The most important question surrounding Dholera is not simply whether the fab produces 50,000 wafers a month.
It is what happens around those wafers.
Does India create enough chip designers to keep the fab busy?
Does it create PDK and IP expertise?
Do Indian universities tape out chips regularly?
Do startups use domestic manufacturing?
Do Indian companies develop reusable IP?
Does software arrive early enough to support new hardware?
Do European and American technology companies participate in the ecosystem?
Do Dutch semiconductor institutions deepen collaboration with Indian universities?
Does ASML's involvement become a pathway for training and R&D rather than merely equipment supply?
Do Indian companies learn to qualify and manufacture increasingly complex products?
These are the questions that determine whether Dholera becomes a fab or becomes an ecosystem.
The most interesting future may not be one giant Indian chip
It may instead be thousands of smaller decisions.
A university chooses RISC-V instead of a proprietary architecture.
A startup adopts an open accelerator.
An engineer contributes a verified PCIe block.
A research team develops a better vector unit.
A government programme funds an MPW shuttle.
A fab develops a better design-enablement flow.
A software company adds another layer of Linux support.
A packaging company develops a better module.
A product company takes all of it and ships something.
Then another company reuses part of that work.
That is how ecosystems compound.
From GitHub to GDSII to Dholera
There is a powerful mental model hiding underneath all of this.
For much of the history of computing, the chain was:
Proprietary architecture → proprietary IP → proprietary fabrication → proprietary software.
The emerging open-silicon model offers another possibility:
Open ISA → open RTL → open verification → open physical-design tools → domestic fabrication → open software.
It will not be completely open.
It does not need to be.
The most practical future is likely to be hybrid.
Open processor cores alongside proprietary PHYs.
Open accelerators alongside licensed memory technology.
Open software alongside proprietary applications.
Domestic manufacturing alongside globally sourced equipment.
Indian design alongside European, American, Taiwanese and Japanese IP.
That is not a weakness.
It is how the modern semiconductor industry actually works.
Conclusion: The open silicon decade
India's semiconductor story is often told as a race to build a fab.
That is only the first chapter.
The more consequential story could be what India chooses to build around that fab.
Dholera provides the manufacturing anchor.
RISC-V provides an open architectural foundation.
SHAKTI demonstrates that India can take an open processor into real silicon.
European projects such as eProcessor demonstrate that open out-of-order RISC-V designs can reach 22nm silicon.
22FDX demonstrates that 22nm FD-SOI can deliver a compelling combination of power, performance, RF integration and cost for the right applications.
Coral NPU, NVDLA and Gemmini show how open acceleration could evolve.
Vortex demonstrates the possibility of open programmable parallel computing.
Fudan's OpenASIC projects show what open video hardware can look like.
Infinite-ISP points toward open imaging.
IIT Madras and OpenSSD projects point toward open storage.
OpenTitan addresses security.
LiteX and related projects address the infrastructure that makes SoCs possible.
OpenROAD attacks the physical-design barrier.
Linux and Ubuntu provide the software foundation.
And the emerging Tata-PSMC-ASML ecosystem connects Indian manufacturing to some of the world's deepest semiconductor expertise. :contentReference[oaicite:10]{index=10}
None of these pieces, individually, creates technological sovereignty.
Together, however, they suggest something much more interesting.
India may not need to invent every component of the semiconductor industry.
It needs to become capable of assembling, modifying, improving and manufacturing enough of the stack that it retains meaningful choice.
That is the opportunity.
And if the story works, then by 2030 we may look back at the present moment not as the beginning of India's semiconductor manufacturing era, but as the beginning of something broader:
India's open silicon era.
The journey could be as simple to describe as four steps:
GitHub → RTL → GDSII → Dholera → silicon.
But the consequence could be much larger.
Because once engineers can repeatedly make that journey, India stops being merely a consumer of computing architectures.
It becomes a participant in creating them.
